Honeywell Aerospace
Portland, OR / Clearwater, FL
1998-Present
International Fortune-100 Company producing products in commercial, aerospace and consumer applications.
Engineer Sr. ASIC, Aerospace Division
Portland, OR
2006-Present
Oversee and support design, verification and synthesis teams in multimillion gate radiation hardened ASIC and FPGA designs.
- Improved GPS Receiver satellite acquisition by a factor of 7 through development of radiation hardened ASIC for use on the NASA Orion Capsule. During EFT-1 Launch, December 2015, GPS tracked 8-12 satellites through apogee, improved over the 0-5 that were expected in that environment.
- Developed GPS Satellite Constellation simulator and ported the Matlab code to SystemVerilog for verification team use. Code allowed variable number of satellites and flight dynamics.
- Backend Synthesis and Static Timing on a legacy ASIC ARM based SoC. Matched timing characteristics of legacy design by extracting legacy timing parameters and generating constraints for the new process. Managed team members (3-5) in Kansas, Minnesota, Florida and Maryland while stationed in Oregon.
- Brought two FPGA designs through DO-254 DAL-A Certification for use in commercial airliners.
- Technical Environment:
- Design and Verification (VHDL, Verilog, System Verilog, C), C Programming, Assembly Programming (ARM), Linux Scripting (bash, perl, python, TCL), Building Cross Compilers (GNU Compiler Chain), SQLite, Makefiles, Version Control via GIT and SVN, Synopsys Design Compiler, PrimeTime and Formality, Mentor Graphics Questasim, MS Project, Visio, Word, Excel, Powerpoint, IBM Rational Doors, Matlab, Microsemi Libero, Xilinx ISE, EMA TimingDesigner, Exceed OnDemand, PuTTY/SSH/SCP, Linux (RHEL; Ubuntu), MS Windows
Engineer Sr., Aerospace Division
Clearwater, FL
2003-2005
Produced FPGA/ASIC designs for commercial, military and space applications, typically for guidance and navigation.
- Designed a novel memory system for satellite based long term RAM storage. Received Patent “Refresh Sequence Control for Multiple Memory Elements” related to this work.
- Technical Environment:
- Design and Verification (VHDL, Verilog, C), C Programming, Linux Scripting (bash, perl, python, TCL), Makefiles, Version Control via SVN, Synopsys Design Compiler, Mentor Graphics Questasim, MS Project, Visio, Word, Excel, Powerpoint, IBM Rational Doors, Matlab, Microsemi Libero, Xilinx ISE, EMA TimingDesigner, Exceed OnDemand, PuTTY/SSH/SCP, Linux (RHEL; Ubuntu), MS Windows
Electrical Engineer II., Aerospace Division
Clearwater, FL
2001-2003
FPGA Design and Verification
- Designed and Verified an FPGA that plays an integral role in Medium Range Missile Defense, currently deployed.
- Technical Environment:
- Design and Verification (VHDL, Verilog), Linux Scripting (bash, perl, python, TCL), Mentor Graphics Modelsim, MS Project, Visio and Office, Linux (RHEL), Unix (HP-UX), MS Windows
Failure Analysis Engineer, Aerospace Division
Clearwater, FL
1998-2001
Performed Root Cause Analysis of product failures in order to suggest ways to improve products.
- Implemented failure analysis on ASICs, discrete components and circuit cards using precision cross sectioning at the IC transistor level, analysis using Scanning Electron Microscopy and chemical decapsulation.
- Technical Environment:
- Scanning electron Microscopy, working with various lab equipment such as an ESD tester, measurement devices, etc., physical sectioning and polishing for individual integrated circuit transistor inspection. Fume Hood and chemical decapsulation, Plasma Etcher.